Written by a stellar team of field experts, this title is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that allow VSLI designers, DFT practitioners, and students to master quickly System-on-Chip Test architectures, memory, and analog/mixed-signal designs.
Read More
Written by a stellar team of field experts, this title is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that allow VSLI designers, DFT practitioners, and students to master quickly System-on-Chip Test architectures, memory, and analog/mixed-signal designs.
Read Less
Add this copy of System-on-Chip Test Architectures: Nanometer Design for to cart. $93.06, new condition, Sold by Just one more Chapter rated 4.0 out of 5 stars, ships from Miramar, FL, UNITED STATES, published 2007 by Morgan Kaufmann.
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Add this copy of System-on-Chip Test Architectures: Nanometer Design for to cart. $117.89, new condition, Sold by paragonbooks rated 4.0 out of 5 stars, ships from Clinton Township, MI, UNITED STATES, published 2007 by Morgan Kaufmann Publishers.
Add this copy of System-on-Chip Test Architectures: Nanometer Design for to cart. $122.93, new condition, Sold by Bonita rated 4.0 out of 5 stars, ships from Santa Clarita, CA, UNITED STATES, published 2007 by Morgan Kaufmann.
